The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
As the semiconductor industry progresses into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of multilayer (or three dimensional) integrated devices. The multilayer devices may include a plurality of interconnect layers each including one or more conductive lines which are interconnected to conductive lines from other interconnect layers through vias. However, as the scaling down continues, vias become smaller and smaller, as do the conductive lines. Thus, forming and aligning the vias to their intended conductive lines from different interconnect layers has become more challenging.
Accordingly, although existing multilayer devices and methods of fabricating multilayer devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.